Arm is introducing two new compute subsystems based on its third generation Neoverse IP. These additions include the Neoverse V3 for high-performance compute workloads like AI and high-frequency trading, and the Neoverse N3 focusing on power efficiency for applications such as telecommunications and networking.
The Neoverse V3, part of Arm’s V-series, boasts the highest single-thread performance in the Neoverse lineup and supports Arm Confidential Computing architecture. With leading private L3 cache sizes, it delivers over a 50% increase in per-socket performance compared to the N2, scaling up to 128 cores per socket.
On the other hand, the Neoverse N3, an extension of the N-series, emphasizes power efficiency. Built on the Arm v9.2 architecture, it features a 2-megabyte per core private L2 cache, supporting PCIe and CXL IO standards and UCIE chiplet standards. The N3 platform offers 32 cores with a TDP as low as 40 watts, showcasing a 20% performance-per-watt improvement over the N2.
Arm’s Total Design initiative has also expanded, now engaging over 20 partners to streamline custom SoC development. This collaborative ecosystem enables seamless delivery of custom SoCs, covering IP verification, firmware customization, and chiplet construction using advanced process nodes.
In the realm of high-performance computing and SoC development, Arm’s advancements with the Neoverse CSS N3 and CSS V3, alongside the growth of the Arm Total Design initiative, signify significant progress. These developments align with the increasing demand for energy-efficient and high-performance computing solutions in industries like AI and cloud computing.
As Arm continues to innovate and collaborate with partners, its influence in shaping future compute architectures, especially in AI-driven technologies, is poised to grow. The company’s efforts to expand its technology integration and cater to evolving market needs position it as a key player in the competitive landscape alongside industry giants like AMD and Intel.
