Data backup and management are seamlessly integrated through innovative chip technology, significantly enhancing efficiency and performance. These cutting-edge chips, designed with a focus on human cognition, are expected to be market-ready within three to five years, necessitating interdisciplinary collaboration to meet business security standards.
Hussam Amrouch has developed an AI-optimized layout that surpasses traditional in-memory computing techniques in potency. The professor at the Technical University of Munich (TUM) leverages a novel computational approach involving ferroelectric field-effect transistors (FeFETs) and specialized circuits, as detailed in the journal Nature. This innovation holds promise for applications in relational AI, deep learning algorithms, and industrial automation in the near future.
The core concept is simple: unlike previous chips that solely performed calculations, the new chips also serve as data storage units, leading to savings in time and energy consumption.
According to Prof. Hussam Amrouch, an expert in AI processor design at TUM, this advancement results in “enhanced chip performance.” By utilizing circuits as small as 28 nanometers, stacked in thousands on each new AI card, the chips aim to deliver faster and more efficient processing capabilities while mitigating heat generation. This feature is crucial for demanding tasks like real-time computations during aircraft operations.
Prof. Hussam Amrouch is spearheading the development of a robust AI platform tailored for energy-intensive applications. Andreas Heddergott/TUM is credited for this achievement.
Enhanced Power and Efficiency of Modern Chips
The metric TOPS/W (tera-operations per second per watt) encapsulates the essential efficiency criteria for chips, serving as a benchmark for their performance. This parameter measures how many trillion operations (TOP) a processor can execute per second (S) with one watt (W) of power.
The new AI chip, a collaborative effort between Bosch and Fraunhofer IMPS, with production support from GlobalFoundries in the US, boasts an impressive efficiency rating of 885TOPS/W. This positions it as twice as potent as leading AI chips, such as Samsung’s MRAM device. In comparison, the operating range of CMOS cards, prevalent in the market, typically falls between 10 to 20TOPS/W. These findings were recently published in Nature.
Chip Design Inspired by Human Brain Architecture
Researchers drew inspiration from the intricacies of the human brain for the contemporary chip architecture. Amrouch elucidates this concept by highlighting how the brain’s neurons process signals while connections retain this information.
The chip incorporates “ferroelectric” (FeFET) transistors to emulate this functionality. These transistors possess the unique ability to retain data even without power and exhibit distinctive characteristics, such as pole reversal upon voltage application. They enable simultaneous data storage and processing within the circuits.
Amrouch emphasizes, “We can now develop highly efficient chipsets suitable for applications like deep learning, cognitive AI, or robotics, where data processing at the source is essential.”
Progress Towards Market Availability
The goal is to expedite data processing from drones during operations, execute deep learning algorithms, and identify objects in space using this technology. However, Prof. Amrouch from TUM’s Munich Institute of Robotics and Machine Intelligence (MIRMI) anticipates a timeline of three to five years before these in-memory chips are commercially viable.
Stringent safety requirements in the business sector contribute to this timeline. For instance, functionality alone is insufficient for deployment in industries like automotive; adherence to industry-specific standards is imperative.
Equipment expert Amrouch underscores the importance of interdisciplinary collaboration, involving experts from various fields like computer science, computing, and electrical engineering. This synergy is deemed a distinctive strength of MIRMI.
